<dfn id="is4kg"></dfn>
  • <ul id="is4kg"></ul>
  • <abbr id="is4kg"></abbr>
  • <ul id="is4kg"></ul>
    <bdo id="is4kg"></bdo>

    曙海教育集團論壇FPGA專區FPGA初中級 → FPGA 時鐘問題


      共有7797人關注過本帖樹形打印

    主題:FPGA 時鐘問題

    美女呀,離線,留言給我吧!
    wangxinxin
      1樓 個性首頁 | 博客 | 信息 | 搜索 | 郵箱 | 主頁 | UC


    加好友 發短信
    等級:青蜂俠 帖子:1393 積分:14038 威望:0 精華:0 注冊:2010-11-12 11:08:23
    FPGA 時鐘問題  發帖心情 Post By:2010-12-19 14:00:46

    剛學不久~

    我要做24H製的時鐘~但我一直DEBUG~一直用不出來~

    Xilinx ISE 8.2i軟體~

    請會的人幫我看一下哪出錯了~謝



    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.STD_LOGIC_ARITH.ALL;

    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    ---- Uncomment the following library declaration if instantiating

    ---- any Xilinx primitives in this code.

    --library UNISIM;

    --use UNISIM.VComponents.all;


    entity CLOCK_00_60 is

        Port ( CLK : in  STD_LOGIC;

               RESET : in  STD_LOGIC;

               ENABLE : out  STD_LOGIC_VECTOR (6 downto 0);

               SEGMENT : out  STD_LOGIC_VECTOR (6 downto 0));

    end CLOCK_00_60;


    architecture Behavioral of CLOCK_00_60 is

    signal SCAN_CLK :STD_LOGIC;

    signal COUNT_CLK :STD_LOGIC;

    signal DECODE_BCD :STD_LOGIC_VECTOR (3 downto 0);

    signal mineable :STD_LOGIC;

    signal hreable :STD_LOGIC;

    signal POSITION:STD_LOGIC_VECTOR (6 downto 0);

    signal DIVIDER:STD_LOGIC_VECTOR (29 downto 1);

    signal COUNT_BCD:STD_LOGIC_VECTOR (23 downto 0);


    begin

    -------------------------------------------------

    process (CLK,RESET)

    begin

    if RESET = '0' then

     DIVIDER <= ( others => '0');

    elsif CLK' event and CLK = '1' then

     DIVIDER <= DIVIDER + 1 ;

    end if;

    end process;

    COUNT_CLK<=DIVIDER(24);

    SCAN_CLK<=DIVIDER(15);

    ------------------------------------------------秒

    process(RESET,SCAN_CLK)

    begin

    if RESET = '0' then

     COUNT_BCD <= ( others => '0');

    elsif SCAN_CLK' event and SCAN_CLK = '1' then

     if   COUNT_BCD(3 downto 0)= x"9" then

        COUNT_BCD(3 downto 0)<= x"0";

        COUNT_BCD(7 downto 4)<= COUNT_BCD(7 downto 4)+1;

     else

       COUNT_BCD(3 downto 0)<= COUNT_BCD(3 downto 0)+1;

     end if;

    end if;

    end process;

    mineable <= '1' when COUNT_BCD(7 downto 0) = x"59" else '0';

    ----------------------------------------------------------分


    process(RESET,SCAN_CLK)

    begin

    if RESET = '0' then

     COUNT_BCD <= ( others => '0');

     if mineable = '1' then

    elsif SCAN_CLK' event and SCAN_CLK = '1' then

     if   COUNT_BCD(11 downto 8)= x"9" then

        COUNT_BCD(11 downto 8)<= x"0";

        COUNT_BCD(15 downto 12)<= COUNT_BCD(15 downto 12)+1;

     else

       COUNT_BCD(11 downto 8)<= COUNT_BCD(11 downto 8)+1;

     end if;

    end if;

    end if;

    end process;

    hreable <= '1' when COUNT_BCD(15 downto 8) = x"59" else '0';

    -------------------------------------------------------------時

    process(RESET,SCAN_CLK)

    begin

    if RESET = '0' then

     COUNT_BCD <= ( others => '0');

      if mineable = '1' and hreable = '1' then

    elsif SCAN_CLK' event and SCAN_CLK = '1' then

     if   COUNT_BCD(19 downto 16)= x"9" then

        COUNT_BCD(19 downto 16)<= x"0";

        COUNT_BCD(23 downto 20)<= COUNT_BCD(23 downto 20)+1;

      if   COUNT_BCD(19 downto 16)= x"2" then

       COUNT_BCD(23 downto 20)<= x"0";

     else

       COUNT_BCD(19 downto 16)<= COUNT_BCD(19 downto 16)+1;

      end if;

     end if;

      end if;

    end if;

    end process;



    process(RESET,SCAN_CLK)

    begin

    if RESET = '0' then

     POSITION <= "1111110";

    elsif SCAN_CLK' event and SCAN_CLK = '1' then

     POSITION<="111111"&POSITION(0);

    end if;

    end process;

    ENABLE<=POSITION;

    -----------------------------------------------------------

    process(POSITION,SCAN_CLK)

    begin

    case POSITION is

     when "1111110" => DECODE_BCD <=COUNT_BCD(3 downto 0);    --秒

     when "1111101" => DECODE_BCD <=COUNT_BCD(7 downto 4);    --秒

     when "1111011" => DECODE_BCD <=COUNT_BCD(11 downto 8);   --分

     when "1110111" => DECODE_BCD <=COUNT_BCD(15 downto 12);   --分

       when "1101111" => DECODE_BCD <=COUNT_BCD(19 downto 16);   --時

       when "1011111" => DECODE_BCD <=COUNT_BCD(23 downto 20);   --時

     when others => null;

    end case;

    end process;

     

    with DECODE_BCD Select

    SEGMENT<= "1000000" when X"0",

      "1111001" when X"1",

      "0100100" when X"2",

      "0110000" when X"3",

      "0011001" when X"4",

      "0010010" when X"5",

      "0000010" when X"6",

      "1111000" when X"7",

      "0000000" when X"8",

      "0010000" when X"9",

      "1111111" when others;


    end Behavioral;

    支持(0中立(0反對(0單帖管理 | 引用 | 回復 回到頂部
    總數 20 1 2 下一頁

    返回版面帖子列表

    FPGA 時鐘問題








    簽名
    主站蜘蛛池模板: 午夜老司机永久免费看片| 处女的第一次电影| 亚洲欧美日韩中文字幕在线一区| 老司机带带我懂得视频| 国产精品夜色一区二区三区| 一边摸一边揉一边做视频| 日本道在线播放| 亚洲欧美成人中文在线网站| 精品一区二区久久久久久久网精 | 国产精品一区二区香蕉| 一区二区三区在线免费看| 无码人妻精品一区二区三18禁| 亚洲日韩乱码中文字幕| 男人的天堂网在线| 国产中文字幕一区| 高清视频一区二区三区| 国内精品伊人久久久久AV一坑| 久久99精品久久久久久不卡| 日本黄色片免费观看| 亚洲欧洲一区二区三区| 激情伊人五月天久久综合| 国产1区2区3区4区| 说女生二哈是什么意思| 国产精品无码无片在线观看| 一区二区三区免费精品视频 | 97色伦图片97综合影院久久| 女仆胸大又放荡的h| 久久人人爽人人爽av片| 日韩精品无码一区二区三区免费 | 欧美色欧美亚洲高清在线视频 | 人人妻人人澡人人爽人人精品浪潮 | 97久久精品无码一区二区| 女人张腿让男桶免费视频大全| 久久久久综合国产| 日韩欧美在线观看视频| 亚洲欧洲精品视频在线观看| 激情内射日本一区二区三区| 同桌一直在夹腿还嗯啊的叫| 色偷偷成人网免费视频男人的天堂 | 自拍另类综合欧美小说| 国产成人精品免费视频软件|